Cadence SSV Release Version 20.17.000 for linux

Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 20.1 production release:

Tempus

Tempus Power Integrity Solution Introduced
The Tempus Power Integrity (Tempus PI) solution integrates the Tempus and Voltus solutions to:
- perform IR-aware timing analysis and failure fixing
- reduce IR drop margins to improve power and area
- utilize proprietary vectorless-based algorithm to identify critical paths most likely impacted by IR drop
Enhanced Support for Integrated Signoff Closure
Tempus Signoff ECO now has the capability to perform DRV, Setup, Hold, and Power Optimization together in the path-based analysis (PBA) mode. This functionality is available through the Innovus cockpit. The new flow enhances user experience by providing easy-to-use Tempus ECO solution. It results in fewer iterations for improving power, performance, and area (PPA).

Voltus

New XP Processing Mode to Achieve Large Capacity and Scalable Performance
Voltus introduces the new Extensively Parallel (XP) mode aimed at providing performance improvements of up to 5X, making it easier to work on giga-scale designs. The XP mode enhances the Voltus solution's massively parallel execution with more efficient scalability on thousands of CPUs and hundreds of machines.
Tempus Power Integrity Flow for IR-Sensitive Path Prediction
The new Tempus Power Integrity (Tempus PI) flow provides a better solution to find and fix IR-sensitive timing paths that result in timing failures. This flow accurately predicts IR drop on the critical paths with Voltus vectorless analysis, and enables automated fixing using Innovus and Tempus IR-ECO.
Simplification of the Vector Profiler Flow
The use model of the Vector Profiler flow has been simplified and streamlined for easy adoption and better usability.
Combined Vector Profiling and Dynamic Power Analysis for Multiple Windows
Supports combining vector profiling and dynamic power analysis to identify windows with maximum activity to further drive dynamic vector-based power analysis.

Silicon signoff and verification (SSV)encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence's signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.